1. Field of the Invention
The present invention relates to a thin film transistor (hereinafter referred to as xe2x80x9cTFTxe2x80x9d) having an interlayer insulating film and to a display using the TFT as a switching element.
2. Description of the Prior Art
Recent development is directed toward TFTs which use a polycrystalline silicon film as an active layer and which are used as a driver element and/or a pixel driving element for an active matrix type liquid crystal display (hereinafter referred to as xe2x80x9cLCDxe2x80x9d) or an organic EL (Electro Luminescence) display.
A conventional TFT is described hereinbelow.
FIG. 1 is a block configuration diagram of a typical LCD.
As shown in the diagram, the LCD comprises a display part provided with TFTS for driving display pixels and a drive circuit for driving the TFTs of the display part, the drive circuit including a scanning side drive circuit 10 and a horizontal side drive circuit 20.
The scanning side drive circuit 10 is provided with a vertical side shift register 11 and a buffer array 12, while the horizontal side drive circuit 20 is provided with a horizontal side shift register 21, a buffer array 22 and a source line switch array 23.
FIG. 2 is a TFT top plane view of a buffer constituting the conventional horizontal side drive circuit 20. FIG. 3 is a sectional view taken along a line 2Axe2x80x942A of FIG. 2.
Referring to FIG. 3, the structure of the TFT of the buffer is described.
On an insulating substrate 510 made of quartz glass or non-alkaline glass, there are formed in the mentioned order a gate electrode 511 made of a refractory metal (high melting point metal) such as chromium (Cr) or molybdenum (Mo), gate insulating film 512 and an active layer 513 made of a polycrystalline silicon film.
The active layer 513 is provided with channels 515 and 516 positioned over the gate electrode 511 and with sources 518 and 521 and drains 519 and 520 which are positioned on both sides of the channels 515 and 516 and which are formed by ion implantation with stoppers 517 serving as masks on the channels 515 and 516. In FIGS. 2 and 3, the TFT on the right of the diagrams is an n-type channel TFT in which impurity ions of phosphorus (P) or the like are doped into the source 518 and the drain 519, whereas the TFT on the left of the diagram is a p-type channel TFT in which impurity ions of boron (B) or the like are doped into the source 521 and the drain 520.
Then, on top of all the surfaces of the gate insulating film 512, active layer 513 and stopper 517 there are formed an interlayer insulating film 522 consisting of an SiO2 film, an SiN film and an SiO2 film which are placed in this order. Metal such as Al is then filled into contact holes provided correspondingly to the sources 518 and 521 and the drains 519 and 520 to thereby form source electrodes 27 and 25 and a drain electrode 24. In this case, the drain electrode 24 connected to the drains 519 and 520 are shared by the n-type channel TFT and the p-type channel TFT. On top of all the surfaces there is further formed a planarization film 26 made of, e.g., organic resin for making the surfaces planar. An inverter 500 consisting of the n-type channel TFT and the p-type channel TFT is thus formed. Another inverter 400 also has the same structure.
Liquid crystal is then filled into the cell gap between the substrate provided with the horizontal side drive circuit including inverters 400 and 500, the vertical side drive circuit and the display pixels, and the substrate confronting the above substrate, to thereby obtain an LCD.
In the conventional TFT, however, impurities from the sealing adhesive occurring upon the positioning to join the two substrates together or impurity ions occurring in the TFT manufacturing steps, may adhere to the top or bottom of the planarization insulating film of the TFT to be charged, with the result that a back channel may be formed in the TFT, causing a variation in the threshold voltage of the TFT. Disadvantageously, this resulted in an increase of the current consumption.
The present invention has been conceived in view of the conventional drawbacks described above. It is therefore the object of the present invention to provide a TFT having a stable threshold voltage as well as a display capable of suppressing an increase in the current consumption, by preventing impurities or other foreign matter from adhering to the top or bottom of the planarization insulating film of the TFT, or even in the case that electric charges are generated.
A TFT of the present invention comprises, on an insulating substrate, a gate electrode, a gate insulating film, a semiconductor film provided with an n-type channel and a source and a drain, an interlayer insulating film, a first electrode connected to the source of the semiconductor film, a second electrode to which a higher voltage than a voltage applied to the first electrode is applied and which is connected to the drain, and a planarization insulating film, said first electrode being disposed in such a manner as to overlap at least the n-type channel.
The above gate electrode is subjected mainly to a relatively low voltage.
A TFT of the present invention comprises, on an insulating substrate, a gate electrode, a gate insulating film, a semiconductor film provided with a p-type channel and a source and a drain, an interlayer insulating film, a first electrode connected to the drain of the semiconductor film, a second electrode subjected to a higher voltage than the voltage applied to the first electrode, the second electrode being connected to the source of the semiconductor film, and a planarization insulating film, wherein the second electrode is disposed in such a manner as to overlap at least the p-type channel.
Further, the above gate electrode is subjected mainly to a relatively high voltage.
A thin film transistor according to another aspect of the present invention comprises a gate electrode, a gate insulating film, a semiconductor film provided with a channel and a source and a drain, an interlayer insulating film, a source electrode connected to the source, and a drain electrode connected to the drain, wherein the source electrode is extended in such a manner as to overlap a channel formation position.
This thin film transistor may employ a configuration in which the channel is a n-type channel, with the gate electrode being subjected to a low level voltage acting as an off voltage for a long period of time.
This thin film transistor may also employ a configuration in which the channel is a p-type channel, with the gate electrode being subjected to a high level voltage acting as an off voltage for a long period of time.
The above thin film transistor can be a bottom gate type transistor having its gate electrode formed under the semiconductor film, with its source electrode covering the top of the channel with the interlayer insulating film therebetween. Alternatively, the above TFT can also be a top gate type transistor having its gate electrode formed over the semiconductor film, with its source electrode extending in such a manner as to cover the top area of the channel of the interlayer insulating film covering the gate electrode and semiconductor film.
In those configurations, according to a further aspect of the present invention, a planarization insulating layer is provided for covering the interlayer insulating film, the source electrode and the drain electrode to thereby flatten the surface.
The thin film transistor subjected to an off voltage for a long period of time is liable to suffer from a variation in characteristics of current and voltage. Thus, by configuring at least the thin film transistor driven in such a condition so that its channel overlaps the source electrode, it is possible to prevent an occurrence of a back channel as a result of accumulation of electric charge attributable to the impurity ions which may invade during the element forming process or upon the production of the display. Further, in spite of possible accumulation of electric charge, the source electrode serves to electrically shield the channel region. This makes it possible to prevent an increase of leakage current at a gate bias of 0 V by the characteristic shift of the thin film transistor.
According to a further aspect of the present invention there is provided a circuit comprising a n-type thin film transistor and a p-type thin film transistor, the n-type thin film transistor including a gate electrode, a gate insulating film, a semiconductor film provided with a n-type channel and a source and a drain, an interlayer insulating film, a source electrode connected to the source, and a drain electrode connected to the drain, the p-type thin film transistor including a gate electrode, a gate insulating film, a semiconductor film provided with a p-type channel and a source and a drain, an interlayer insulating film, a source electrode connected to the source, and a drain electrode connected to t the drain, wherein the n-type thin film transistor and the p-type thin film transistor share the gate electrode and the drain electrode, with respective source electrodes being connected to different power sources to provide a complementary connection structure, and wherein the source electrode of either the n-type thin film transistor or the p-type thin film transistor, that is, whichever one is subjected for a longer period of time to an off voltage, applied to the shared gate electrode, for turning that transistor off, extends in such a manner as to overlap a channel formation region of corresponding thin film transistor.
The above n-type and p-type thin film transistors of the above circuit can be a bottom gate type thin film transistor or a top gate type thin film transistor.
In such a so-called CMOS structure circuit, a voltage for turning the transistor off is applied to the shared gate electrode of either of the n-type and p-type thin film transistors which are connected to each other in a complementary manner. Then, in particular, the thin film transistor subjected to the off voltage for a longer period of time may be very likely to suffer from a characteristic variation due to the occurrence of a back channel. Thus, by electrically protecting the channel region by the source electrode of the present invention, the variation in characteristics can be reliably prevented.
According to a yet further aspect of the present invention, the above thin film transistor is used as an element of a display.
Further, according to a still further aspect of the present invention there is provided a display having a plurality of pixels which are arranged in a matrix manner and which are controlled for display, wherein a channel of either n-type or p-type thin film transistors connected in a complementary manner to at least a drive circuit for feeding a display signal to each pixel among drive circuits of the display, that is, a channel of either n-type or p-type thin film transistor having at least gate electrodes subjected for a longer period of time to a voltage for turning those transistors off, extends in such a manner as to overlap the source electrode with the interlayer insulating film therebetween.
In a flat display such as a liquid crystal display or an organic electroluminescence (EL) display, arrangement is such that switching elements (thin film transistors) of the display part and a drive circuit for driving the switching elements are formed on the same substrate. In such a case, the drive circuit often employs the CMOS structure of thin film transistors having the same configuration as the display thin film transistors. Variations in characteristics of the thin film transistors constituting the drive circuit may act directly on the display quality of the display. In the case of a drive circuit (e.g., a horizontal drive circuit) which feeds a display signal to each pixel in particular, the variations in characteristics may have a significant influence on the characteristics of the unit due to its rapid operation speed. It is therefore very important to prevent the variations in characteristics of the thin film transistors of the drive circuit.
Further, in the case of employing the CMOS structure, one of the n-type and p-type thin film transistors is necessarily turned off upon operation of the unit, so that the transistors having a longer off state are liable to suffer from characteristic variations due to the occurrence of a back channel.
In the process for building the display, formation of the thin film transistors precedes rubbing on the planarization insulating film and enclosure of liquid crystal material in the case of the liquid crystal display or the formation of the EL element part in the case of the organic EL display, all of which may increase the possibility allowing the invasion of impurity ions causing accumulation of electric charge.
In such a situation, the present invention is arranged such that with respect to the transistor having a longer off state among the CMOS structured transistors, a channel and a source electrode thereof overlap each other so that the channel is electrically shielded by the voltage of the source electrode, thereby securely and effectively hindering a back channel liable to occur without causing any increase in the production steps, to consequently achieve a secure prevention of variations of characteristics of the thin film transistors.
According to the present invention as described above, it is possible to prevent impurities from adhering to the top of the TFTs (e.g., on the planarization insulating film) and to impede a shift of characteristics of the TFT attributable to the undesired adhesion. It is also possible to provide TFTs having stabilized threshold voltage and to suppress an increase in the current consumption. Further, use of such TFTs in the display achieves prevention of increase in current consumption of the unit as well as a satisfactory display.